View CY28322-2_416563.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
CY28322-2
133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs
Features * Compliant with Intel CK-Titan and CK-408 clock synthesizer/driver specifications * Multiple output clocks at different frequencies -- Two pairs of differential CPU outputs, up to 200 MHz -- Nine synchronous PCI clocks, three free-running -- Six 3V66 clocks -- Two 48-MHz clocks -- One reference clock at 14.318 MHz -- One VCH clock * Spread Spectrum clocking (down spread) * Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#) * 48-pin TSSOP package Enables reduction of EMI and overall system cost Enables ACPI-compliant designs
Benefits Supports next generation Pentium processors using differential clock drivers Motherboard clock generator -- Support multiple CPUs and a chipset -- Support for PCI slots and chipset -- Supports AGP, DRCG reference, and Hub Link -- Supports USB host and graphic controllers -- Supports ISA slots and I/O chip
* Two select inputs (Mode select & IC Frequency Select) Supports up to four CPU clock frequencies Widely available, standard package enables lower cost
Logic Block Diagram
VDD_REF
PWR
Pin Configurations
TSSOP Top View
XTAL_IN XTAL_OUT GND_REF PCI_F0 PCI_F1
Stop Clock Control
X1 X2
XTAL OSC
1 2 3 4 5 6 7 8 9 10
48 47 46 45 44 43 42 41 40 39
VDD_REF REF0 S1 CPU_STOP# VDD_CPU CPU1 CPU#1 GND_CPU VDD_CPU CPU2 CPU#2 IREF S2 USB DOT VDD_48 MHz GND_48 MHz 3V66_1/VCH PCI_STOP# 3V66_0 VDD_3V66 GND_3V66 SCLK SDATA
REF
PLL Ref Freq PLL 1
S1:2 PWR_GD# CPU_STOP# Gate Divider Network
PWR
VDD_CPU CPU1:2 CPU#1:2
PCI_F2 GND_PCI PCI0 PCI1 PCI2 VDD_PCI PCI3 PCI4 PCI5
CY28322-2
PWR Stop Clock Control
VDD_PCI PCI_F0:2 PCI0:5
11 12 13 14 15 16 17 18 19 20 21 22 23 24
38 37 36 35 34 33 32 31 30 29 28 27 26 25
PCI_STOP# PWR_DWN#
PWR
/2
VDD_3V66 3V66_0:1
PWR
VDD_3V66 GND_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 66IN/3V66_5 PWR_DWN# VDD_CORE GND_CORE PWR_GD#
3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN
PLL 2
VDD_48MHz
PWR
USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1
SDATA SCLK
SMBus Logic
Cypress Semiconductor Corporation Document #: 38-07145 Rev. *B
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 14, 2002
PRELIMINARY
Pin Summary
Pin Name REF0 XTAL_IN XTAL_OUT CPU, CPU# [1:2] 3V66_0 3V66_1/VCH 66IN/3V66_5 PCI_F [0:2] PCI [0:5] USB DOT S2 S1 IREF PWR_DWN# PCI_STOP# CPU_STOP# PWRGD# 47 1 2 43, 39, 42, 38 29 31 20 4, 5, 6 35 34 36 46 37 21 30 45 24 Pin Number 3.3V 14.318-MHz clock output 14.318-MHz crystal input 14.318-MHz crystal input Differential CPU clock outputs 3.3V 66-MHz clock output 3.3V selectable through SMBus to be 66 MHz or 48 MHz Pin Description
CY28322-2
66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO 33 MHz clocks divided down from 66Input or divided down from 3V66 Fixed 48-MHz clock output Fixed 48-MHz clock output Special 3.3V 3-level input for Mode selection 3.3V LVTTL inputs for CPU frequency selection A precision resistor is attached to this pin which is connected to the internal current reference 3.3V LVTTL input for Power_Down# (active LOW) 3.3V LVTTL input for PCI_STOP# (active LOW) 3.3V LVTTL input for CPU_STOP# (active LOW) 3.3V LVTTL input is a level sensitive strobe used to determine when S[2:1] inputs are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored. SMBus compatible SDATA SMBus compatible Sclk
66BUFF [2:0] /3V66 [4:2] 17, 18, 19
8, 9, 10, 12, 13, 14 PCI clock outputs divided down from 66Input or divided down from 3V66
SDATA SCLK VDD_PCI, VDD_3V66, VDD_CPU,VDD_REF VDD_48 MHz VDD_CORE
25 26
11, 15, 28, 40, 44, 3.3V power supply for outputs 48 33 22 3.3V power supply for 48 MHz 3.3V power supply for PLL
GND_REF, GND_PCI, 3, 7, 16, 27, 32, 41 Ground for outputs GND_3V66, GND_IREF, GND_CPU GND_CORE 23 Ground for PLL
Function Table[1]
S2 1 1 0 0 Mid Mid S1 0 1 0 1 0 1 CPU (MHz) 100 MHz 133 MHz 100 MHz 133 MHz TCLK/2 Reserved 3V66[0:1] (MHz) 66 MHz 66 MHz 66 MHz 66 MHz TCLK/4 Reserved 66BUFF[0:2]/3 V66[2:4] (MHz) 66IN 66IN 66 MHz 66 MHz TCLK/4 Reserved 66IN/3V66_5 (MHz) 66 MHz Input 66 MHz Input 66 MHz 66 MHz TCLK/4 Reserved PCI_F/PCI (MHz) 66IN/2 66IN/2 33 MHz 33 MHz TCLK/8 Reserved REF0(MHz) 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz TCLK Reserved USB/DOT (MHz) 48 MHz 48 MHz 48 MHz 48 MHz TCLK/2 Reserved Notes 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 7, 8, 5 -
Notes: 1. TCLK is a test clock driven in on the XTALIN input in test mode. 2. "Normal" mode of operation 3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz. 4. Frequency accuracy of 48 MHz must be +167 PPM to match USB default. 5. Mid is defined a voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V. 6. Required for DC output impedance verification. 7. These modes are to use the same internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock margining. 8. All parameters specified with loaded outputs.
Document #: 38-07145 Rev. *B
Page 2 of 17
PRELIMINARY
Clock Driver Impedances
Impedance Buffer CPU, CPU# REF PCI, 3V66, 66BUFF USB DOT 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 VDD Range Buffer Type Type X1 Type 3 Type 5 Type 3A Type 3B 20 12 12 12 Min. Typ. 50 40 30 30 30
CY28322-2
Max. 60 55 55 55
Clock Enable Configuration
PWR_DWN# CPU_STOP# PCI_STOP# 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 CPU IREF*2 IREF*2 IREF*2 ON ON CPU# FLOAT FLOAT FLOAT ON ON 3V66 LOW ON ON ON ON 66BUFF LOW ON ON ON ON PCI_F LOW ON ON ON ON PCI LOW OFF ON OFF ON USB/DOT LOW ON ON ON ON VCOS/ OSC OFF ON ON ON ON
Serial Data Interface (SMBus)
To enhance the flexibility and function of the clock synthesizer, a two signal SMBus interface is provided according to SMBus specification. Through the Serial Data Interface, various device functions such as individual clock output buffers, can be individually enabled or disabled. CY28322-2 supports both block read and block write operations. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte, (most significant bit first) with the Start Slave Address R/W Bit 1 1 0 1 0 0 1 0 0/1 1 bit 7 bits 1 A Command Code 00000000 8 bits
ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a WRITE condition. The R/W bit is used by the SMBus controller as a data direction bit. A zero indicates a WRITE condition to the clock device. The slave receiver address is 11010010 (D2h). A command code of 0000 0000 (00h) and the byte count bytes are required for any transfer. After the command code, the core logic issues a byte count which describes number of additional bytes required for the transfer, not including the command code and byte count bytes. For example, if the host has 20 data bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes It may not be 0. Figure 1 shows an example of a block write. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. ... Data Byte N-1 A Stop Bit 8 bits 1 1 bit
A Byte Count = A Data Byte 0 A N 1 8 bits 1 8 bits 1
1
From Master to Slave From Slave to Master Figure 1. An Example of a Block Write
Document #: 38-07145 Rev. *B
Page 3 of 17
PRELIMINARY
Data Byte Configuration Map
Data Byte 0: Control Register (0 = Enable, 1 = Disable) Bit Bit 7 Affected Pin# Name Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On
CY28322-2
Type R/W
Power-on Default 0
4, 5, 6, 10, PCI [0:6] 11, 12, 13, CPU[2:1] 16, 17, 18, 3V66[1:0] 33, 35 - 31 TBD 3V66_1/VCH
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TBD VCH Select 66 MHz/48 MHz 0 = 66 MHz, 1 = 48 MHz CPU_STOP# Reflects the current value of the external CPU_STOP# pin PCI_STOP# (Does not affect PCI_F [2:0] pins) S2-Reflects the value of the S2 pin sampled on power-up S1-Reflects the value of the S1 pin sampled on power-up Reserved
R R/W R R/W R R R
0 0 N/A N/A N/A N/A 1
39, 43, 38, CPU [2:1] 42 CPU# [2:1] 8, 9, 10, 11, PCI [5:0] 12, 13, 14, - - - - - -
Pin# - 43,39, 38, 39 42, 43 - 38, 39 42, 43 - N/A CPU1:2 CPU2 CPU2# CPU1 CPU1#
Name CPU Mult0 Value
Description Three-state CPU1:2 during power-down 0 = Normal; 1 = Three-stated Allow Control of CPU2 with assertion of CPU_STOP# 0 = Not free running; 1 = Free running Allow Control of CPU1 with assertion of CPU_STOP# 0 = Not free running;1 = Free running Reserved CPU2 Output Enable 1 = Enabled; 0 = Disabled CPU1Output Enable 1 = Enabled; 0 = Disabled Reserved
Type R R/W R/W R/W R/W R/W R/W R/W
Power-on Default N/A 0 0 0 0 1 1 1
Reserved CPU2 CPU2# CPU1 CPU1# Reserved
Pin# N/A 14 13 12 10 9 8 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0
Name N/A
Pin Description PCI5 Output Enable 1 = Enabled, 0 = Disabled PCI4 Output Enable 1 = Enabled; 0 = Disabled PCI3 Output Enable 1 = Enabled; 0 = Disabled PCI2Output Enable 1 = Enabled; 0 = Disabled PCI1 Output Enable 1 = Enabled; 0 = Disabled PCI0 Output Enable 1 = Enabled; 0 = Disabled Write to"0"
Type R R/W R/W R/W R/W R/W R/W R/W
Power-on Default 0 1 1 1 1 1 1 1
Reserved
Document #: 38-07145 Rev. *B
Page 4 of 17
PRELIMINARY
Data Byte 3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data Byte 4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Pin# - - 29 31 20 Name TBD TBD 3V66_0 3V66_1/VCH 66IN/3V66_5 N/A N/A 3V66_0 Output Enable 1 = Enabled; 0 = Disabled 3V66_1/VCH Output Enable 1 = Enabled; 0 = Disabled 3V66_5 Output Enable 1 = Enable; 0 = Disable Note. This bit should be used when pin 24 is configured as 3v66_5 output. Do not clear this bit when pin 24 is configured as 66IN input. 66-MHz Buffered 2 Output Enable 1 = Enabled; 0 = Disabled 66-MHz Buffered 1 Output Enable 1 = Enabled; 0 = Disabled 66-MHz Buffered 0 Output Enable 1 = Enabled; 0 = Disabled Pin Description Pin# 34 35 6 5 4 6 5 4 DOT USB PCI_F2 PCI_F1 PCI_F0 PCI_F2 PCI_F1 PCI_F0 Name Pin Description DOT 48-MHz Output Enable USB 48-MHz Output Enable Allow control of PCI_F2 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# Allow control of PCI_F1 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# Allow control of PCI_F0 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# PCI_F2 Output Enable PCI_F1Output Enable PCI_F0 Output Enable
CY28322-2
Power-on Default 1 1 0 0 0 1 1 1
Type R/W R/W R/W R/W R/W R/W R/W R/W
Type R R R/W R/W R/W
Power-on Default 0 0 1 1 1
Bit 2 Bit 1 Bit 0
19 18 17
66BUFF2 66BUFF1 66BUFF0
R/W R/W R/W
1 1 1
Data Byte 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 6: Vendor ID Bit Bit 7 Bit 6 Bit 5 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Description Type R R R Power-on Default 0 0 0 Pin# N/A N/A 66BUFF [2:0] 66BUFF [2:0] DOT DOT USB USB USB edge rate control DOT edge rate control Name N/A N/A Tpd 66IN to 66BUFF propagation delay control Pin Description Type R R R/W R/W R/W R/W R/W R/W Power-on Default 0 0 0 0 0 0 0 0
Document #: 38-07145 Rev. *B
Page 5 of 17
PRELIMINARY
Byte 6: Vendor ID (continued) Bit Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Type R R R R R
CY28322-2
Power-on Default 0 1 0 0 0
Document #: 38-07145 Rev. *B
Page 6 of 17
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5
CY28322-2
Storage Temperature (Non-condensing) .... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation...............................................1 Static Discharge Voltage ........................................................ (per MIL-STD-883, Method 3015) ............................ > 2000V
Operating Conditions[9] Over which Electrical Parameters are Guaranteed
Parameter VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_CPU, VDD_48 MHz TA Cin CXTAL CL Description 3.3V Supply Voltages 48-MHz Supply Voltage Operating Temperature, Ambient Input Pin Capacitance XTAL Pin Capacitance Max. Capacitive Load on USBCLK, REF PCICLK, 3V66 Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 2.85 0 Max. 3.465 3.465 70 5 22.5 20 30 14.318 MHz Unit V V C pF pF pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VOH VOL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input High Current Input Low Current High-level Output Current Except Crystal Pads USB, REF, 3V66 PCI USB, REF, 3V66 PCI 0 < VIN < VDD 0 < VIN < VDD CPU For IOH =6*IRef Configuration REF, DOT, USB 3V66, DOT, PCI IOL Low-level Output Current REF, DOT, USB 3V66, PCI IOZ IDD3 IDDPD3 IDDPD3 IDDPD3 Output Leakage Current 3.3V Shutdown Current 3.3V Shutdown Current 3.3V Shutdown Current Three-state VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA (Byte1, Bit [6] = 0) VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA (Byte1, Bit [6] = 0) VDD_CORE/VDD3.3 = 3.465V (Byte1, Bit [6] = 1) Type X1, VOH = 0.65V Type X1, VOH = 0.74V Type 3, VOH = 1.00V Type 3, VOH = 3.135V Type 5, VOH = 1.00V Type 5, VOH = 3.135V Type 3, VOL = 1.95V Type 3, VOL = 0.4V Type 5, VOL =1.95 V Type 5, VOL = 0.4V 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 30 38 10 360 25 45 1.5 mA mA mA mA mA 29 27 -33 -33 mA -29 -23 IOH = -1 mA IOH = -1 mA IOL = 1 mA IOL = 1 mA -5 -5 12.9 14.9 2.4 2.4 0.4 0.55 5 5 Test Conditions Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 Min. Max. Unit 2.0 0.8 V V V V V V mA mA mA
Document #: 38-07145 Rev. *B
Page 7 of 17
PRELIMINARY
-
CY28322-2
Switching Characteristics[8] Over the Operating Range
Parameter t1 t3 t3 t5 t5 t6 t7 t9 t9 t9 t9 t2 t3 t4 t8 Voh Vol Vcrossover All USB, REF, DOT PCI,3V66 3V66[0:1] 66BUFF[0:2] PCI 3V66, PCI 3V66 USB, DOT PCI REF CPU CPU CPU CPU CPU CPU CPU CPU Output Description Output Duty Cycle[9] Falling Edge Rate Falling Edge Rate 3V66-3V66 Skew 66BUFF-66BUFF Skew PCI-PCI Skew 3V66-PCI Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Rise Time Fall Time CPU-CPU Skew Cycle-Cycle Clock Jitter Rise/Fall Matching High-level Output Voltage including overshoot Low-level Output Voltage including undershoot Crossover Voltage Test Conditions Measured at 1.5V Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at 1.5V Measured at 1.5V Measured at 1.5V 3V66 leads. Measured at 1.5V Measured at 1.5V t9 = t9A - t9B Measured at 1.5V t9 = t9A - t9B Measured at 1.5V t9 = t9A - t9B Measured at 1.5V t9 = t9A - t9B Measured differential waveform from -0.35V to +0.35V Measured differential waveform from -0.35V to +0.35V Measured at Crossover Measured at Crossover t8 = t8A - t8B Measured with test loads Measured with test loads
[11] [12]
Min. 45 0.5 1.0
Max. 55 2.0 4.0 500 175 500
Unit % ns V/ns ps ps ps ns ps ps ps ps ps ps ps ps mV V V V
1.5
3.5 250 350 500 1000
CPU 1.0V Switching Characteristics 175 175 467 467 150 150 325 0.92 -0.2 0.51 1.45 0.35 0.76
Measured with test loads[12] Measured with test loads[12]
Notes: 9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 10. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 11. Determined as a fraction of 2*(Trp - Trn)/(Trp +Trn) where Trp is a rising edge and Trn is an intersecting falling edge. 12. The 1.0V test load is shown on test circuit page.
Document #: 38-07145 Rev. *B
Page 8 of 17
PRELIMINARY
Definition and Application of PWRGD# Signal
Vtt
CY28322-2
VRM8.5 PWRGD#
CPU
BSEL0
BSEL1
3.3V 3.3V
NPN
3.3V
PWRGD#
CLOCK GENERATOR
S0
10K
10K
GMCH
S1 10K 10K
Document #: 38-07145 Rev. *B
Page 9 of 17
PRELIMINARY
Switching Waveforms
Duty Cycle Timing (Single-ended Output)
t1B t1A
CY28322-2
Duty Cycle Timing (CPU Differential Output)
t1B t1A
All Outputs Rise/Fall Time
VDD 0V t2 t3
OUTPUT
CPU-CPU Clock Skew
Host_b Host Host_b Host t4
3V66-3V66 Clock Skew
3V66
3V66
t5
Document #: 38-07145 Rev. *B
Page 10 of 17
PRELIMINARY
Switching Waveforms (continued)
PCI-PCI Clock Skew
PCI
CY28322-2
PCI t6
3V66-PCI Clock Skew
3V66
PCI t7
CPU Clock Cycle-Cycle Jitter
t8A Host_b Host t8B
Cycle-Cycle Clock Jitter
t9A t9B
CLK
Document #: 38-07145 Rev. *B
Page 11 of 17
PRELIMINARY
PWRDWN# Assertion
CY28322-2
66BUFF PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF
UNDEF Power-down Rest of Generator
Note: PCI_STOP# asserted LOW
PWRDWN# Deassertion
<3 ms
66BUFF1/GMCH 66BUFF0,2 PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF
10-30 s min. 100-200 s max.
Note: PCI_STOP# asserted LOW
Document #: 38-07145 Rev. *B
Page 12 of 17
PRELIMINARY
PWRGD# Timing Diagrams
CY28322-2
GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM PWRGD# FROM NPN VCC CPU CORE PWRGD# VCC W320 CLOCK GEN CLOCK STATE State 0 OFF CLOCK VCO OFF CLOCK OUTPUTS ON
0.2 -- 0.3 ms Wait for delay PWRGD# Sample BSELS
Possible glitch while Clock VCC is coming up. Will be gone in 0.2-0.3 mS delay.
State 1
State 2
State 3 ON
Figure 2. CPU Power BEFORE Clock Power
GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM PWRGD# FROM
VCC CPU CORE PWRGD# VCC W320 CLOCK GEN CLOCK STATE State 0 OFF CLOCK VCO OFF LOCK OUTPUTS ON ON
0.2 - 0.3 ms delay Wait for PWRGD# Sample BSELS
State 1
State 2
State 3
Figure 3. CPU Power AFTER Clock Power
Document #: 38-07145 Rev. *B
Page 13 of 17
PRELIMINARY
Layout Example
+3.3V Supply FB
VDDQ3
F 0.005 F
CY28322-2
C1 G
G
1 2 3 4 5 6 7 8 9
10
G
G
G V
G
G
V G G G V G
G
G
11 V 12 G 13 14 15 V 16 G 17 18 19 G 20 21 G Core 22 V 23 G 24 G
G G G
*Option A
G G
G V G
G
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
G
G
G
FB = Dale ILB1206-300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S Ferrite bead Ceramic Caps C1 = 10-22 F G = VIA to GND plane layer C2 = 0.005 F C5 = 0.1 F C6 = 10 F V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors. * If on board video uses 48-MHz or Dot clock add the Option B 8 series resistor All Bypass cap's on VDD pin = 0.1 F Low ESR
CY28322-2
VDDQ3 8
*Option B
C5 G
G C6
G
Document #: 38-07145 Rev. *B
Page 14 of 17
PRELIMINARY
Test Circuit
VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU
CY28322-2
3, 7, 16, 27, 32, 41 11, 15, 28, 40, 44, 48
1.0V Test Load 33 2 pF
Test Node 20 pF
Ref,USB Outputs
CY28322-2
CPU OUTPUTS
475
33
Test Nodes
2 pF
Test Node 30 pF
PCI,3V66 Outputs
1.0V Amplitude
63.4
63.4
Ordering Information
Ordering Code CY28322ZC-2 48-pin TSSOP Package Type Operating Range Commercial
Document #: 38-07145 Rev. *B
Page 15 of 17
PRELIMINARY
Package Diagram
CY28322-2
48-pin Thin Shrink Small Outline Package
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07145 Rev. *B
Page 16 of 17
(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY28322-2
Document Title: CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Document Number: 38-07145 REV. ** *A *B ECN NO. 112664 114703 122796 Issue Date 03/01/02 04/29/02 12/14/02 Orig. of Change IKA INA RBI New Data Sheet Corrections on some PIN numbers. Add Power up Requirements to Operating Conditions Information Description of Change
Document #: 38-07145 Rev. *B
Page 17 of 17

▲Up To Search▲

Price & Availability of CY28322-2

	To Download CY28322-2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .